Integrated circuits are integrating more and more different functional units, with the scale of integration continually increasing. This means that, by way of example, the different transmission and receiver assemblies which need to be integrated into mobile radios are arranged in just one, fully integrated transceiver chip. This integrated circuit integrates one or more phase locked loops (PLLs), voltage-controlled oscillators (VCOs), mixer cells, and in some cases even filter units.
Each of these assemblies, of which there are many present on a chip, normally has control signals applied to it externally, for example from a baseband chip, when the chip is turned on or else during operation, in order to select particular modes of operation, to set frequencies, to perform calibration operations etc. It is obvious that it is not possible to route all of these control lines to the outside. Rather, there is normally a programming interface which can be used to address the internal functions. Since, although the individual assemblies on the chip need to be controlled, no information needs to be read from the chip, this interface is normally in the form of a serial, one-way interface.
One option for implementing such a control bus with little involvement is the “three-wire bus”. This affords sufficient speed, little protocol involvement during operation and relatively simple implementation. The three lines in the three-wire bus normally comprise a clock line, a data line and an enable line.
An integrated circuit having a plurality of function groups which can be programmed via a three-wire bus, as described, is shown in FIG. 3. This figure contains a three-wire bus 1, 2, 3 comprising a data line 1, a clock line 2, and an enable line 3 for the purpose of programming a plurality of different assemblies. By way of example, just two assemblies are shown in this case. Each assembly has an associated shift register 4, 5 for programming the assembly, said shift register comprising an address part and a data part. By way of example, the address part comprises three bits and the data part comprises 21 bits. The parallel output for the 21 data bits has a respective transfer register 6, 7 connected to it for reading the data from the shift registers 4, 5 on the basis of a transfer signal, which is provided by a respective decoder 8, 9. The decoders each have four inputs, which are connected firstly to the enable line 3 of the three-wire bus and secondly to the three address bits of the associated shift register 4, 5. On the output side, the decoders 8, 9 provide a respective transfer signal and supply it to the control input of the transfer register 6, 7 which control input is connected to the output. This transfer signal is provided at the precise point at which the enable signal from the three-wire bus is present and the address matches the address of the respective shift register 4, 5.
The allocation of programming data to a particular assembly is accordingly performed using address bits in a “programming word”. The actual transfer of the data to the internal registers in the assemblies is performed by virtue of the enable line becoming inactive. In the case of the present embodiment, the shift registers 4, 5 respectively all accept the same and each programming word. The allocation of a programming word to the respective assembly is performed on the basis of the address, with only one selected transfer register ever transferring the data to the respective assembly in each case.
The chip architecture means that the maximum number of bits which a programming word can comprise is normally limited, for example in the present case to 24 bits. A further restriction on the maximum volume of information which can be transmitted for the chip which is to be programmed arises on account of the time sequence conditions which are stipulated in the respective specifications, which conditions permit the transmission of just a relatively small number of programming words in succession in a defined time frame.
On the other hand, as already explained, the number of different functional units integrated on a chip is large and increasing, and it is also an aim to be able to program these functional units independently of one another.
The increasing complexity of the functions integrated on a chip, on the one hand, with the aim of setting a large number of operation-dependent parameters, and a limited number of address and data bits, on the other hand, mean that the bits which are available for test modes of operation in the integrated circuit are becoming fewer and fewer.
On the other hand, it is normally necessary to be able to test all of the functions of an integrated circuit during production, however. This requires that particular functional units be put into suitable operating states in order to allow measurements. In addition, it is often necessary to measure functional units in a signal chain individually and independently of one another. This requires that these functional units be able to be activated in special test modes of operation. For test purposes, it is also an aim to be able to turn on numerous special operating states.
A solution to this problem could be obtained by altering the metallization layers during the production of the integrated circuit in order to obtain appropriate settings such that particular functions are added or removed by adding or omitting pieces of interconnect. However, this requires additional, undesirable involvement during production and a further drawback in that the test options are significantly restricted in terms of flexibility.